In contrast to traditional planar metal-oxide-semiconductor field-effect transistors (MOS transistors or MOSFETs), which are fabricated using conventional lithographic fabrication methods, nonplanar MOSFETs incorporate various vertical transistor structures. One such semiconductor structure is the “FinFET,” which takes its name from the multiple thin silicon “fins” that are used to form the respective gate channels, and which are typically on the order of tens of nanometers in width.
The prior art is replete with different techniques and processes for fabricating MOS transistor semiconductor devices, including both planar and non-planar devices. In accordance with typical fabrication techniques, a MOS transistor integrated circuit is formed by creating a device structure on a semiconductor substrate, where the device structure includes a gate stack formed on a layer of semiconductor material, and source and drain regions formed in the semiconductor material to define a channel region under the gate stack. Some integrated circuit devices are fabricated using a “replacement” gate technique; in accordance with this technique, temporary gate material (typically polycrystalline or amorphous silicon) is removed, temporarily forming a trench-like structure (hereinafter “trench”), and then replaced (filled) with a different “replacement” gate metal.
In recent years, a principal focus for improved MOS transistor performance has been increasing the mobility and drive current in the transistor. The demand for ever increasing performance and switching speed of integrated circuits requires continuously higher carrier mobility and drive currents. One approach to this problem is to introduce continuously higher channel stresses in order to achieve higher carrier mobility and drive currents. However, many stressors lose their effectiveness for three-dimensional device architectures, such as FinFET architectures. Another approach involves the use of a channel material with intrinsically higher carrier mobility than silicon including, for example, the various group III-V semiconductor alloys such as InP or GaAs, or group IV semiconductor materials such as Ge. However, a problem with using these “new” channel materials lies in the process integration into an existing silicon-compatible fabrication flow. That is, the handling of new substrate materials (compared to silicon) requires significant changes in processing (etching, cleaning, etc.), which is typically prohibitively expensive for use in large-scale fabrication operations.
Accordingly, it is desirable to provide FinFET structures and methods for fabricating FinFET structures with improved carrier mobility and drive current. It is further desirable to provide methods for fabricating such FinFET structures that do not have significant fabrication cost increases over those currently employed in the art. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings, the brief summary, and this background of the invention.